In the past, Al—Cu and its related alloys were the preferred alloys for forming interconnections on electronic devices such as integrated circuit chips. The amount of Cu in Al—Cu is typically in the range of 0.3 to 4 percent.
Replacement of Al—Cu by Cu and Cu alloys as chip interconnection materials results in advantages of performance. Performance is improved because the resistivity of Cu and certain copper alloys is less than the resistivity of Al—Cu; thus narrower lines can be used and higher wiring densities will be realized.
The advantages of Cu metallization have been recognized by the semiconductor industry. In fact, the semiconductor industry is rapidly moving away from aluminum and is adopting copper as the material of choice for chip interconnects because of its high conductivity and improved reliability.
Manufacturing of chip interconnects involves many process steps that are interrelated. In particular, copper interconnects are manufactured using a process called “Dual Damascene” in which a via and a line are fabricated together in a single step. An integration issue that needs to be overcome to successfully fabricate Dual Damascene copper interconnects is the adhesion of the barrier to seed layer films and to the copper interconnects. In addition, the International Technology Roadmap for Semiconductors, 1999 Edition, calls for small via diameters and higher aspect ratios in future interconnect metallizations.
In may prior art techniques, copper is electrodeposited on a copper seed layer which in turn is deposited onto a diffusion layer. Both diffusion barrier and Cu seed layer are typically deposited using physical vapor deposition (PVD), ionized physical vapor deposition (IPVD), or chemical vapor deposition (CVD) techniques (Hu et al. Mat. Chem. Phys., 52 (1998)5). Moreover, the diffusion barrier is frequently composed of two layers (e.g. Ti/TiN bilayer barrier).
Accordingly, room exists for improvement in the prior art for improving the adhesion to the seed layer or copper layers.